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74ABTL3205 10-bit BTL transceiver with registers
Product specification 1995 Jun 16
Philips Semiconductors
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
FEATURES
* 10-bit BTL transceiver * Drives heavily loaded backplanes with equivalent load
impedances down to 10 ohms
DESCRIPTION
This transceiver is a 10 bit bidirectional transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading (<6pF) by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. To support live insertion, OEB is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. The LOGIC VCC and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together. This transceiver function is intended to operate in a half-duplex mode. Low current in standby mode is obtained by powering down unused circuitry. Likewise, transmit circuitry is powered down when in receive mode and receive circuitry is powered down while in transmit mode.
* High drive 100mA BTL open collector drivers on B-port * Allows incident wave switching in heavily loaded backplane buses * Reduced BTL voltage swing produces less noise and reduces
power consumption
* Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
* Compatible with IEEE Futurebus+ or proprietary BTL backplanes * Controlled output ramp and multiple GND pins minimize ground
bounce
* Tight output skew (0.5nsec typical) * Glitch-free power up/down operation * Low ICC current * Supports live insertion * High density packaging * ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL COB IOL Propagation delay An to Bn Propagation delay Bn to An Output capacitance (B0 - B8) only) Output current (B0 - B8) only) Standby ICC Supply current An to Bn Bn to An PARAMETER TYPICAL 3.3 3.7 3.6 3.5 6 100 1 7 18 mA UNIT ns ns pF mA
ORDERING INFORMATION
PACKAGES 52-PIN PQFP TEMPERATURE RANGE -40C to +85C OUTSIDE NORTH AMERICA 74ABTL3205 BB NORTH AMERICA 74ABTL3205 BB DWG NUMBER SOT379-1
1995 Jun 16
2
853-1802 15352
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
PIN CONFIGURATION
BUS GND TTL Gnd AClk1 AClkin Recmode OEA1 OEA2 BClk1 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 AFP A7 APAR IEA Transmode BUS GND BG VCC BG GND Power Up TTL Gnd VCC M/S B7 BiasV Mode
VCC
OEB
52 TTL Gnd A0 A1 TTL GND A2 A3 TTL GND AClk2 TTL GND A4 A5 TTL GND A6 1 2 3 4 5 6 7 8 9 10 11 12 13
51 50 49 48 47 46 45 44 43 42 41 40 BUS GND B0 B1 BUS GND B2 B3 BUS GND BClk2 BUS GND B4 B5 BUS GND B6
VCC
SA00138
PIN DESCRIPTION
SYMBOL OEA1 OEA2 OEB IEA M/S FUNCTION Output enable data receiver group 1 Output enable data receiver group 2 Output enable data transmitter Output enable clock and framepulse receiver Master/Slave select: L: Master, enable clock transmitter H: Slave, disable clock transmitter Low: High: Power Up Recmode Tranmode AClk1 AClkln Data through mode Registered data mode Low High High Input Input Input I/O I/O TTL TTL TTL TTL TTL ASSERTION Low Low Low Low I/O Input Input Input Input Input LOGIC TTL TTL TTL TTL TTL
Mode
Input
TTL
Power up mode, held low during power up to disable clock and data transmitters Enables receiver Enables transmitter Clock or data path IEA = H Input for busclock IEA = L Output for busclock data group 1 Clock or data path Alternate data path Alternate data path data group 2 Clock or data path data group 1 Clock or data path data group 2
A0..A3 AClk2 AFPIn APAR A4..A7 BClk1 B0..B3 BClk2 B4..B7
I/O I/O Output Input I/O I/O I/O I/O I/O
TTL TTL TTL TTL TTL BTL BTL BTL BTL
1995 Jun 16
3
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LOGIC DIAGRAM
ACLKin I/O
ACLK1 I/O
BCLK1 I/O
ACLK2 I/O
AFP OUT
APAR IN
D C
Q
BCLK2 I/O
B0-B3 A0-A3 I/O I/O D C Q
B4-B7 A4-A7 I/O I/O D C IEA IN OEB IN M/S IN OEA1 IN OEA2 IN RECMODE IN MODE IN TRANMODE IN POWERUP IN Definition for the MUX: Q
Low
High
SA00139
1995 Jun 16
4
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
FUNCTION TABLE
INPUTS MODE An to Bn (REGISTERED) AN to Bn (THROUGH) B0-B3 to A0-A3 AA (THROUGH) B4-B7 to A4-A7 AA (THROUGH) ACLK1 to BCLK1 ACLK2 to BCLK2 BCLK1 to ACLK1 BCLK2 to ACLK2 APAR to BCLK2 BCLK2 to AFPIn BCLK1 to ACLKin An I h L H O O O O X X X X X X X X X X X X X X Bn O O O O L H L H X X X X X X X X X X X X X X ACLK in X X X X X X X X X X X X X X X X O O ACLK 1 X X X X X X X X L H X X O O X X X X X X X X ACLK 2 X X X X X X X X X X L H X X O O X X X X X X BCLK 1 X X X X X X X X O O X X L H X X X X X X L H BCLK 2 X X X X X X X X X X O O X X L H X X L H X X OEA1 H H H H L L X X H H X X L L X X X X X X H H OEA2 H H H H X X L L X X H H X X L L X X X X H H OEB L L L L H H H H X X H H X X X X L L X X L L APAR X X X X X X X X X X X X X X X X I h X X O O IEA H H X X X X X X X X X X X X X X X X L L L L M/S X X X X X X X X L L L L X X X X H H X X H H MODE H H L L X X X X X X L L X X X X H H X X H H REC MODE L L L L H H H H X X X X H H H H X X H H L L TRAN MODE H H H H L L L L H H H H L L L L H H L L H H POWER UP H H H H L L L L H H H H X X X X H H X X H H
OUTPUTS MODE O An to Bn (REGISTERED) AN to Bn (THROUGH) B0-B3 to A0-A3 AA (THROUGH) B4-B7 to A4-A7 AA (THROUGH) ACLK1 to BCLK1 ACLK2 to BCLK2 BCLK1 to ACLK1 BCLK2 to ACLK2 APAR to BCLK2 BCLK2 to AFPIn BCLK1 to ACLKin An Input Input Input Input H L H L X X X X X X X X X X X X X X Bn H* L H* L Input Input Input Input X X X X X X X X X X X X X X ACLK in X X X X Input Input Input Input X X X X X X X X Input Input X X H L ACLK1 X X X X X X X X Input Input X X H L X X X X X X X X ACLK2 X X X X X X X X X X Input Input X X H L X X X X X X BCLK1 X X X X X X X X H* L X X Input Input X X X X X X Input Input BCLK2 X X X X X X X X X X H* L X X Input Input H* L Input Input X X AF Pin X X X X X X X X X X X X X X X X X X H* L X X
NOTES: H = High voltage level L = Low voltage level h = High voltage level one set-up time prior to Low to High ACLKin transition l = Low voltage level one set-up time prior to Low to High ACLKin transition = Low to High transition Z = High impedance (off) state H* = Goes to level of pull-up voltage X = Don't care O = Output
1995 Jun 16
5
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LOGIC SYMBOL (IEEE/IEC)
Recmode Transmode Powerup OEA1 OEA2 OEB IEA M/S MODE EN1 EN2 EN3 EN4 EN5 EN6 6C7
&
EN8
AClk1 AClkIn A0 A1
1 4 1 1 7D 7D 7D 7D
5
BClk1
3 3 3 3 5
B0 B1 B2 B3 BClk2
A2 A3 AClk2 AFP APAR A4 A5 A6 A7
1 1 2 4
7D 2 2 2 2 7D 7D 7D 7D
8 3 3 3 3 B4 B5 B6 B7
SA00140
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IO OUT Tamb TSTG Supply voltage TTL Signals Input voltage BTL Signals Input current Voltage applied to output in High output state A0 - A8 Current applied to output in Low output state B0 - B8 Operating free-air temperature range Storage temperature 200 -40 to +85 -65 to +150 mA C C -1.2 to +5.5 -18 to +5 -0.5 to +VCC 48 V mA /v mA PARAMETER RATING -0.5 to +7.0 -1.2 to +7.0 UNIT V V
1995 Jun 16
6
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL IOH IOFF PARAMETER High level output current Power-off output current BTL BTL TEST CONDITIONS1 MIN VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V VCC = MIN, VIL = MAX,4 VIH = MIN, IOH = -3mA VOH High-level output voltage TTL VCC = MIN to MAX, 4 VIL = MAX, VIH = MIN, IOH = -10A VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA VIK II In ut clam Input clamp voltage Input current at maximum input voltage TTL BTL TTL TTL IIH Hi h l l input current t t High-level i BTL TTL BTL Off-state output current Off-state output current Short-circuit output current3 TTL TTL TTL Recmode Low Tranmode Low Recmode Low Tranmode High ICC Supply current (total) Recmode Low Tranmode High Recmode High Tranmode Low Recmode High Tranmode High VCC = MIN, II = IIK VCC = MIN, II = -18mA VCC = MAX, VI = 0.5V or 5.5V VCC = MAX, VI = 2.7V, Bn = AIn = 0V VCC = MAX, VI = 1.9V VCC = MAX, VI = 3.5V5 VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.75V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX, VO = 0.0V VCC = MAX VCC = MAX Mode = Low VCC = MAX Mode = High VCC = MAX VCC = MAX -60 100 0.1 0.1 0.1 20 130 1 7 13 18 29 -20 -100 50 -50 -150 3 12 21 25 43 0.75 0.5 0.35 1.0 0.7 0.8 0.8 0.1 0.1 0.1 -1.2 -1.2 50 20 100 2.5 LIMITS TYP2 0.5 10 2.85 MAX 100 100 3.4 A A V UNIT
VCC - 1.1 0.5 1.10
V
TTL VOL Low-level output voltage BTL
V V V V V mA mA mA mA mA mA mA
IIL IOZH IOZL IOS
Low-level in ut current input
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100A, but the parts will continue to function normally. TTL signals CLKin, CLK-1/CLK-OUT, CLK-2/FP-OUT, /FP-IN, /PARITY t,A0..A7, OEB, MASTER/SLAVE, MODE, OEA1, OEA2 BTL signals CLK1BTL, CLK2BTL, B0..B7
1995 Jun 16
7
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LIVE INSERTION SPECIFICATIONS
LIMITS SYMBOL VBIASV Bias pin DC current PARAMETER VCC = 0 to 5.25V, Bn = 0 to 2.0 V VCC = 0 to 4.75 V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V IBIASV Bias pin DC current in VCC = 4.5 to 5.5V, Bn = 0 to 2.0 V, Bias V = 4.5 to 5.5V B0 - B8 = 0V, Bias V = 5.0V 1.62 MIN 4.5 NOM MAX 5.5 1 10 2.1 UNIT V mA A V
Bn
Bus voltage during prebias
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = 5V CL = 50pF, CL = 500 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPLZ tPHZ tPLZ tTLH tTHL tSK(p) Propagation delay g y Bn to An Propagation delay, g y BCLK1 to ACLK1 Propagation delay g y BCLK1 to ACLKin Propagation delay g y BCLK2 to ACLK2 Propagation delay g y BCLK2 to AFP Output Enable time OEA1, OEA2, IEA to An Output Disable time OEA1, OEA2, IEA to An Output transition time, An Port 10% to 90%, 90% to 10% Pulse skew2 |tPHL - tPLH| MAX Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 1 2 1, Waveform 4 5 4, Test Circuit and Waveforms Waveform 3 2.0 2.0 1.8 2.0 1.8 2.0 1.8 2.0 1.8 2.0 1.8 2.0 1.8 1.6 2.0 TYP 3.6 3.5 3.8 3.6 3.7 3.7 3.7 3.9 3.8 3.9 3.8 2.5 2.5 3.3 MAX 6.5 6.1 6.5 6.1 6.5 6.1 6.5 6.1 6.5 6.1 6.5 6.1 5.6 7.8 Tamb = -40C to +85C VCC = 5V 10% CL = 50pF, CL = 500 MIN 2.0 1.8 2.0 1.8 2.0 1.8 2.0 1.8 2.0 1.8 2.0 1.8 1.4 1.8 3.0 1.7 MAX 7.3 6.7 7.3 6.7 7.3 6.7 7.3 6.7 7.3 6.7 7.3 6.7 5.7 8.2 7.0 4.0 ns ns ns ns ns ns ns ns ns UNIT
NOTES: 1. | tPN actual - tPM actual | for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 Jun 16
8
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
AC ELECTRICAL CHARACTERISTICS
B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = 5V CD = 30pF, RU = 18.5 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(p) Propagation delay g y An to Bn Propagation delay, g y ACLKin to Bn Propagation delay g y ACLKin to BCLK2 Propagation delay g y ACLK1 to BCLK1 Propagation delay g y ACLK2 to BCLK2 Enable/disable time OEB to Bn or BCLK2 Transition time, Bn Port (1.3V to 1.8V) Pulse skew2 |tPHL - tPLH| MAX Waveform 2 Waveform 1 2 1, Waveform 1 2 1, Waveform 2 Waveform 2 Waveform 1 2 1, Test Circuit and Waveforms Waveform 3 1.0 1.0 2.0 2.0 2.0 2.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.6 2.0 TYP 3.3 2.7 4.6 4.5 4.6 4.5 3.2 2.9 3.1 3.1 3.8 3.4 MAX 4.7 4.5 5.9 5.9 7.3 7.3 4.7 4.5 5.7 5.5 6.8 6.4 2.5 2.0 Tamb = -40C to +85C VCC = 5V 10% CL = 30pF, RU = 18.5 MIN 1.0 1.0 2.0 2.0 2.0 2.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.6 MAX 5.7 57 6.3 6.3 7.6 7.6 5.1 4.7 6.0 5.6 7.6 6.9 3.0 2.5 ns ns ns ns ns ns UNIT
ns ns
NOTES: 1. | tPN actual - tPM actual | for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).
AC SETUP REQUIREMENTS
LIMITS TEST CONDITION Tamb = +25C VCC = 5V Tamb = -40C to +85C VCC = 5V 10%
SYMBOL
PARAMETER
UNIT
CL = 50pF (A side) / CD = 30pF (B side) RL = 500 (A side) / RU = 18.5 (B side) MIN TYP MIN 2.0 1.5 2.3 2.0 MAX ns ns
ts(H) ts(L) th(H) th(L)
Setup time An to ACLKin Hold time An to ACLKin
Waveform 6 Waveform 6
1.9 1.3 1.8 2.0
1995 Jun 16
9
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
AC WAVEFORMS
VM = 1.55V for Bn, VM = 1.5V for all others
VM OEAn tPLH
VM
OEA
VM tPZH
VM tPHZ VOH -0.3V 0V
tPHL An VM VM
VM
An
SA00144 SA00141
Waveform 1. Propagation Delay for Data or Output Enable to Output
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
OEA VM An, Bn tPHL Bn, An VM VM tPLH VM
VM tPZL
VM tPLZ
An
VM
VOL +0.3V
SA00145
SA00142
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
Waveform 2. Propagation Delay for Data to Output
An, Bn
VM
tSK(0)
An, Bn
VM
SA00143
Waveform 3. Output Skews
1995 Jun 16
10
EEE EEEE EEE EEE EEEE EEE EEE EEEE EEE
An or Bn VM VM VM VM tS(H) th(H) tS(L) th(L) ACLKin VM VM
SA00349
Waveform 6. Data Setup and Hold Times
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
TEST CIRCUIT AND WAVEFORMS
VCC BIAS V RL tW 90% VM 10% tTHL (tF) tTLH (tR) 90% 90% VM tW 10% LOW V 10% LOW V tTLH (tR) tTHL (tF) AMP (V) VM AMP (V) 7.0V
VIN PULSE GENERATOR RT D.U.T.
VOUT
90% CL RL NEGATIVE PULSE
Test Circuit for 3-State Outputs on A Port SWITCH POSITION TEST tPLZ, tPZL All other SWITCH closed open
POSITIVE PULSE 10% VM
VM = 1.55V for Bn or Bn, VM = 1.5V for all others
VCC BIAS V 2.0V (for RU = 9) 2.1V (for RU = 16.5)
Input Pulse Definition INPUT PULSE REQUIREMENTS Amplitude A Port 3.0V 2.0V Low V 0.0V 1.0V Rep. Rate 1MHz 1MHz tW tTLH tTHL 2.5ns 2.5ns
VIN PULSE GENERATOR RT D.U.T.
VOUT
RU
ABTL
500ns 2.5ns 500ns 2.5ns
CD
B Port
Test Circuit for Outputs on B Port DEFINITIONS RL = CL = RT = CD = RU = Load resistor; see AC CHARACTERISTICS for value. Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. Termination resistance should be equal to ZOUT of pulse generators. Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. Pull up resistor; see AC CHARACTERISTICS for value.
SA00146
1995 Jun 16
11
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
1995 Jun 16
12
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
NOTES
1995 Jun 16
13
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 01-00 Document order number: 9397 750 06827
Philips Semiconductors
1995 Jun 16 14

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